IWCN 2021: Computational Research of CMOS Channel Material Benchmarking for Future Technology Nodes: Missions, Learnings, and Remaining Challenges

By raseong kim1, Uygar Avci1, Ian Alexander Young1

1. Components Research, Intel Corporation, Hillsboro, OR

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Abstract

In this abstract, we review our journey of doing CMOS channel material benchmarking for future technology nodes. Through the comprehensive computational research for past several years [1-7], we have successfully projected the performance of various novel material CMOS based on rigorous physics models, and we have also obtained new physical insights and learnings on the key design considerations for extremely scaled n- and pMOS transistors. There are, however, still research gaps and challenges remaining to complete the whole picture and provide an ultimate theoretical guidance on the material choice for future CMOS, as will be discussed at the end of this abstract.

For the model device, we considered double-gate (DG) or gate-all-around (GAA) nanowire (NW) MOSFETs with the gate length (LG) of 13 nm for various n- and pMOS materials (Fig. 1). We first showed that it is essential to optimize the device design depending on each material. As shown in Fig. 2, it is critical to optimize the source/drain (S/D) design such as the tip doping density (Ntip) to balance the source exhaustion [8] vs. tunneling leakage for materials with small effective mass (m*) and bandgap, such as III-V’s and Ge [1, 9]. For materials with multiple valleys (Γ, L, and X), it is also important to optimize the crystal orientation [10, 11]. In Fig. 3, we show that quantum confinements in Ge NW nMOS with [110] transport may result in optimum density-of-states (DOS) and injection velocity, providing good ballistic performance topping Si or III-V nMOS [3].

Another important issue is the carrier transport model. To simulate the upper limit of current drivability, ballistic transport model has been widely used in many benchmarking studies [12, 13]. Even for extremely scaled devices (LG≲15 nm), however, carrier scattering effects may be still significant [14]. While it is also critical to consider quantum transport effects such as tunneling in extremely scaled devices, it is very expensive numerically to incorporate scattering effects within a quantum transport simulation framework. In this study, to capture both effects of quantum transport and carrier scattering, we take a hybrid approach [6], by calculating the so-called “ballistic ratio” (BR) [15] from full-band Monte Carlo (MC) simulations [16, 17] and applying them as correction factors to the ballistic current-voltage (I-V) from atomistic quantum transport simulation [18-20] (Fig. 4).

While many benchmarking studies focus on the I-V characteristics of intrinsic devices, parasitic components such as S/D resistance (RSD) may critically impact the actual performance. We have included realistic values of RSD in most of our benchmarking studies, and we also showed that RSD may also significantly depend on the S/D contact geometry due to the carrier scattering and momentum distribution effects [5], especially for light m* materials such as III-V nMOS (Fig. 5). We also note that in addition to I-V’s, capacitance-voltage (C-V) and circuit performance metrics such as the effective drive current (Ieff) [21], switching energy (CV2), and switching delay (CV/I) including relevant parasitics (such as RSD and parasitic capacitance (Cpar)) and loading effects (gate or wire capacitance loading) are as important to correctly compare various CMOS combinations (homogeneous or heterogeneous) [4, 6] as shown in Fig. 6. We also note that for some channel materials such as Ge, we may have different S/D designs (e.g. Ntip’s) that provide optimum performance for the given operation target (high performance or low power).

Finally, while most of previous studies have been done at room temperature (T), we showed that the higher operating T’s for circuits and systems [22] may have significant implications regarding CMOS benchmarking, especially for novel channel materials (Fig. 7) [7]. Due to different T-dependences of thermionic vs. tunneling leakages, for example, performance metrics such as the maximum supply voltage (VDD,max) may increase at high T, providing improved Ieff in a wider range of VDD while still satisfying Si-like leakage power conditions [7, 23].

While we have achieved significant benchmarking results for novel CMOS channel materials, there are still research gaps to be filled. First, while we introduced a hybrid approach [6] by combining results from two different simulation tools (quantum ballistic (fundamental) + MC (correction factors)) to capture both effects of quantum transport and carrier scattering, the research community may develop a more unified way (e.g. a new, numerically efficient approach to incorporate scattering into the quantum simulation framework) to accurately include those effects within a single, self-consistent simulation tool. Also, while we did consider some circuit aspects in our 2 benchmarking (Ieff, CV , CV/I, operating T’s), more in-depth simulations for the process and circuits may be done to analyze the material impact on the layout, fabrication, and system-level performance (“system-technology co- optimization”). This may be particularly important because novel CMOS channel materials may not only promise performance boost for individual transistors but also give integration challenges to the existing Si-based technology.

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Cite this work

Researchers should cite this work as follows:

  • raseong kim, Uygar Avci, Ian Alexander Young (2021), "IWCN 2021: Computational Research of CMOS Channel Material Benchmarking for Future Technology Nodes: Missions, Learnings, and Remaining Challenges," https://nanohub.org/resources/35265.

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