Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model 1.0.0

By Zizhen Jiang1, H.-S. Philip Wong1

Stanford University

The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM.

Listed in Compact Models | publication by group NEEDS: Nano-Engineered Electronic Device Simulation Node

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Version 1.0.0 - published on 23 Oct 2014 doi:10.4231/D37H1DN48 - cite this

Licensed under NEEDS Modified CMC License according to these terms

Description

The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM. In principle, this model has no limitations on the size of the RRAM cell. The complex process of ion and vacancy migration was simplified into the growth of a single dominant filament that preserved the essential switching physics. The size of the tunneling gap (g), which is the distance between the tip of the filament and the opposite electrode, is the primary variable determining device resistance. The current conduction is exponentially dependent on the tunneling gap distance. This distance is found by calculating the growth of the gap, taking into consideration the electric field, temperature-enhanced oxygen ion migration, and local temperature due to Joule heating. In addition, stochastic and temperature-dependent filament movement (δg) is also included. The RRAM model can be instantiated directly in HSPICE netlists to explore the impacts of RRAM on the circuit performance. It is an accurate and handy tool for design exploration and verification of RRAM circuits.

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Key References

Jane Zizhen Jiang; Shimeng Yu; Yi Wu; Jesse H. Engel; Ximeng Guan; H. –S P. Wong, “Verilog-A Compact Model for Oxide-based Resistive Random Access Memory,” SISPAD 2014, submitted

Shimeng Yu; Bin Gao; Zheng Fang; Hongyu Yu; Jinfeng Kang; , H.-S. P. Wong, "A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling," Electron Devices Meeting (IEDM), 2012 IEEE International , vol., no., pp.10.4.1,10.4.4, 10-13 Dec. 2012, doi: 10.1109/IEDM.2012.6479018

Ximeng Guan; Shimeng Yu; H.-S. P ,Wong, "A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations," Electron Device Letters, IEEE , vol.33, no.10, pp.1405,1407, Oct. 2012, doi: 10.1109/LED.2012.2210856

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