PN Junction Lab

This tool enables users to explore and teach the basic concepts of P-N junction devices.

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Version 1.9.2 - published on 23 Jul 2014

doi:10.4231/D3GH9B95N cite this

This tool is closed source.

First-Time User Guide View All Supporting Documents

 

Newer version available

Newer version available

This resource has a newer version available at https://nanohub.org/resources/36260

    SCREENSHOT #1 PN junction in forward bias mode SCREENSHOT #3 SCREENSHOT #4 DEMO #1

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Tools

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Abstract

PN Junction Lab - This tool enables users to explore and teach the basic concepts of P-N junction devices. Edit the doping concentrations, change the materials, tweak minority carrier lifetimes, and modify the ambient temperature. Then, see the effects in the energy band diagram, carrier densities, net charge distribution, I/V characteristic, etc. Tutorial on PN Junction Theory and modeling is found on the following links: Some interesting exercises regarding pn-junction theory and modeling are listed below:
      Improvements / modifications in subsequent version releases:
  • 1.9.1 - Updated material specifications based on ASF Vol.6 R.F.Pierret for Si,Ge and GaAs
  • 1.9 - Added InP material specifications
  • 1.8 - Added option to add impurity doping in the Intrinsic region.
  • 1.7.1 - Fixed for saving previous result with node number changed.
  • 1.7 - Fixed for equilibrium Recombination rate (/cm3). Improved meshing with large node points.
  • 1.6 - Fixed for improved meshing in PIN diode case. Fixed Recombination (/cm3) rate sign.
  • 1.53 - Meshing improved by adding doping dependence on mesh density.
  • 1.52 - Improved meshing using inhomogenous grid.
  • 1.51 - Corrected excess minority carrier error.
  • 1.5- Added depletion approximation.
  • 1.4 - Added status bar for running simulation.
  • 1.3.1 - Updated the output plot labeling.
  • 1.3 - Added Current Density (A/cm2) plot in output for each bias in sequence.
  • 1.2.2 - Increased the input Voltage (V) range for simulations.
  • 1.2.1 - Fixed for post-run deletion of redundant output files.
  • 1.2 - Added CV (Capacitance-Voltage) curve in the output plot. CV across PN junction can now be visualized
  • 1.1.2 - Updated for meshing density for faster convergence.
  • 1.1.1 - Updated for minimum number of nodes to be used in simulation.
  • 1.1 - Fixed minor bug in bias point discrepancy . Converted bias points from integer to float
  • 1.0 - 1D PN-Junction tool launched.

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PADRE (Pisces And Device REplacement) developed by Mark Pinto at AT&T Bell Labs.

Cite this work

Researchers should cite this work as follows:

  • www.eas.asu.edu/~vasilesk

  • Dragica Vasileska, Matteo Mannino, Michael McLennan, Xufeng Wang, Gerhard Klimeck, Saumitra Raj Mehrotra, Benjamin P Haley (2014), "PN Junction Lab," https://nanohub.org/resources/pntoy. (DOI: 10.4231/D3GH9B95N).

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Tags

  1. ACUTE
  2. drift-diffusion
  3. microelectronics
  4. nanoelectronics
  5. NCN Group - Semiconductor Device Physics
  6. NCN@Purdue Supported
  7. Padre
  8. pn-junction
  9. PN Junction Lab