III-V Nanoscale MOSFETS: Physics, Modeling, and Design
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Abstract
As predicted by the International Roadmap for Semiconductors (ITRS), power consumption has been the bottleneck for future silicon CMOS technology scaling. To circumvent this limit, researchers are investigating alternative structures and materials, among which III-V compound semiconductor-based quantum-well field effect transistors stand out as one of the most promising device candidates for future high-speed, lowpower digital logic applications, because their light effective masses lead to high electron mobilities and high on-current, which should translate into high device performance at low supply voltage. For such nanoscale devices, both atomistic and quantum effects become important in determining their electronic structure and transport properties. Detailed modeling and simulation that captures these effects will be essential to help understand and provide guidance to device design and optimization. In this work, III-V transistors are studied from a simulation perspective. A 20-band sp3d5s*-SO semiempirical atomistic tight-binding model is used to study the bandstructure effects in the performance projection of III-V transistors. The C-V characteristics of GaAs MOS capacitor is studied from simulation, the simulation results were related to explaining the experimental observations. As a promising candidate for post-Si CMOS application, the III-V HEMTs devices are studied from simulation with focuses on device analysis and careful benchmarking against experimental data. The simulation and analysis at room temperature show that the III-V HEMTs with gate length less than 100nm operate quite close to their ballistic limits. The temperature-dependent study reveals that the transconductance's characteristic at different temperatures could be fully explained with ballistic device physics without involving phonon scattering. Next, the ballistic injection velocity is examined with simulation and compared to results extracted from I-V/C-V data. Results show that the injection velocity from the top of the barrier can be lower than that from the virtual source due to the pre-existing charge at the channel/source junction at on-state, and will be affected by several factors including the source design. Finally, a design study to assess the III-V vs. Si MOSFETs performance at 12 and 8nm nodes shows that III-V may outperform Si at both technology nodes due to the performance degradation in Si FETs from scattering.
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Yang Liu received his PhD at Purdue University in December 2010.
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Purdue University, West Lafayette, IN