NOTE: This course is currently in production. New lectures will be available as they are produced.

Digital integrated circuits used in electronic computing systems (including cell phones, personal computers, servers, wearable devices, network routers and automotive electronics) are entirely or largely designed using Electronic Design Automation (EDA) tools. EDA, which is also referred to as Computer Aided Design (CAD), has been a key enabler to the semiconductor, electronics and computing industries. An understanding of how EDA tools work is essential for IC designers (EDA tool users) who wish to get the most of the tools, as well as to developers of EDA tools. In addition, the algorithms and computational techniques used in EDA tools have found wide applicability in many other application domains.

This course provides an introduction to the tools used to design and analyze digital circuits at the logic level of abstraction (where circuits are composed of gates and flip-flops). The course explores EDA tools by abstracting the underlying computational problems and presenting exact and heuristic algorithms that are used to solve them. Topics covered include an overview of the integrated circuit design flow, advanced Boolean algebra, synthesis of two-level circuits, multi-level logic synthesis and technology mapping, sequential circuit synthesis, formal verification, timing analysis and optimization, power analysis and reduction, and design tools for emerging nanoscale technologies.

Principal Topics (Units)

1. Introduction to EDA: Overview of Integrated Circuit (IC) design flow and levels of abstraction in IC design, Quick tour through design automation at the logic level. (1 week)
2. Advanced Boolean Algebra: Representations of Boolean functions, Operations on Boolean functions, Co-factors and their applications, Unate functions and unate-recursive paradigm. (1 week)
3. Two-level logic synthesis: Re-cap of K-maps and Quine McCluskey method, Covering as a core problem in EDA, Exact and heuristic covering algorithms, Efficient generation of prime implicants, Heuristic two-level synthesis. (3 weeks)
4. Multi-level logic synthesis: Boolean networks, Transformations on Boolean networks, Factoring, Algebraic and Boolean division, Kernel-based factoring, Efficient factoring using 0-1 matrices, Satisfiability and Observability don't cares, Optimization using don't cares, Technology mapping, Multi-level synthesis in practice. (3 weeks)
5. Sequential synthesis: Finite-State Machine Synthesis – State minization and Encoding, Structural sequential optimization with Retiming (1 week)
6. Timing Analysis: Clocking models for sequential circuits, Delay models for gates, Topological timing analysis, Functional timing analysis and the false path problem. (1 week)
7. Timing Optimization: Collapsing and Re-structuring, Delay optimizing circuit transforms, Eliminating false paths, Technology mapping for minimum delay. (1 week)
8. Combinational and Sequential Verification: Equivalence checking and model checking, Binary Decision Diagrams, Efficient function manipulation and analysis using BDDs, Use of BDDs for verification, Boolean Satisfiability Algorithms and Applications to Verification. (2 weeks)
9. Low power design: Power estimation, Technology mapping for low power, Clock gating, Power management at the logic level (operand isolation, guarded evaluation and pre-computation) (2 weeks)
10. Current topics: Variation-aware design, Design for nanoscale technologies. (1 week)

Anand Raghunathan received the B. Tech. degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Madras, India, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ. He is currently the Silicon Valley Professor and Chair of the VLSI area in the School of Electrical and Computer Engineering at Purdue University. He serves as Associate Director of the $36M SRC/DARPA Center for Brain-inspired Computing (C-BRIC) and founding co-director of the Purdue/TSMC Center for a Secured Microelectronics Ecosystem (CSME). His research explores brain-inspired computing, energy-efficient and high-performance machine learning, system-on-chip design and computing with post-CMOS devices. He holds a Distinguished Visiting Chair at the Indian Institute of Technology, Madras, where he is helping establish a Center for Computational Brain Research. He is a co-founder of High Performance Imaging, Inc., a company commercializing Purdue innovations in the area of computational imaging. Before joining Purdue, he was a Senior Researcher and Project Leader at NEC Laboratories America and held a visiting position at Princeton University.

Secondary Reading List

• Synthesis and Optimization of Digital Circuits, G. De Micheli, Kluwer Academic Publishers, 2006, ISBN-13 No. 978-0070582781.
• Logic Synthesis and Verification, G. D. Hachtel and F. Somenzi, Kluwer Academic Publishers, 2006, ISBN-13 No. 978-0387310046.
• Logic Synthesis, S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill Professional, ISBN-13 No. 978-0070165007, June 1994.

Researchers should cite this work as follows:

• Anand Raghunathan (2023), "ECE 512: Digital Systems Design Automation," https://nanohub.org/resources/36792.

  BibTex | EndNote

1. design automation
2. integrated circuits
3. SCALE affiliated